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| Advance PM8355 QuadPHY-IITM 4-Channel 2.125, 2.5 and 3.125 Gbit/s Transceiver with Half-rate Support GENERAL DESCRIPTION The QuadPHY-II is a physical layer transceiver ideal for systems requiring high speed point-to-point communication links. It is applicable for PMAPMD connections in 10 GE, Infiniband 1 or 4 x 2.5 Gbit/s links, 1 and 2 Gbit/s Fibre Channel, as well as high speed serial backplanes for high capacity systems. SERIAL I/O * Redundant high speed serial I/O channels for convenient switching to redundant fabric. * High speed outputs with optional preemphasis to drive longer backplanes. * High speed I/O with on-chip termination resistors to directly drive dual-terminated 50 Ohm lines. TEST FEATURES * Extensive control of loopback, BIST, and operating modes via 802.3 compliant MDC/MDIO serial interface. * On-chip packet generator/checkerprovides at-speed diagnostics. * Built-in error counters per channel. * Support for IEEE 1149.1 JTAG testing on all pins. FEATURES GENERAL * 10Gbit/s, bi-directional, XAUI to XGMII link supporting the proposed IEEE 802.3ae (the standard is draft and is subject to change). * Four independent 2.125, 2.5 and 3.125 Gbit/s Serdes for Fibre Channel, Infiniband, 10 GE line cards and highspeed backplane applications. * Half/Full rate mode selectable per channel. * Integrated serializer/ deserializer, clock synthesis, clock recovery and 8B/10B encode/decode logic. * Under 2 Watts typical power. PARALLEL I/O * 10-bit Dual Data Rate (DDR) parallel interface. * Selectable source simultaneous or source synchronous transmit and receive parallel interfaces. * Convenient output clock for user friendly ASIC timing. * Interoperates with SSTL2 and 1.8V LVCMOS standard. PHYSICAL * 1.8V, 0.18 micron standard CMOS technology with 2.5V tolerant I/O. * 289-ball PBGA (19mm x 19mm package). APPLICATIONS * * * * * * High speed serial backplanes 10 GE links Fibre Channel transceivers Infiniband transceivers XAUI retimers Intra-system interconnect TRUNKING &TIMING * Integrated Receive FIFO synchronizes incoming data to local clock domain. * Trunking feature de-skews and aligns all four channels to form a single 10 Gbit/s logical link. BLOCK DIAGRAM Transmit Channel A (1 of 4) TXD[9:0] TDOXP/ TDOXN TDOYP/ TDOYN (per channel) 2 Serializer 2 TXCLK (shared) Receive Channel A (1 of 4) 10B/8B Decoder 8 or 10 FIFO & Trunking Logic RXD[9:0] (per channel) 9 or 10 RXCLK (per channel) 10 8B/10B Encoder FIFO & /A/ insert Adaptive Sampler (per channel) 9 or 10 RDIXP/ RDIXN RDIYP/ RDIYN (per channel) 2 Clock Recovery 2 Deserialize & Byte Align Common Control Logic RESET, MDC, MDIO Mode strapping pins JTAG interface BIST pins Clock Synthesizer SYSCLK (1x or 2x rate) PLL_LOCK SYSCLK RATE PMC-2000791 (A4) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE REFCLK (c) Copyright PMC-Sierra, Inc. 2001 Advance PM8355 QuadPHY-IITM 4-Channel 2.125, 2.5 and 3.125 Gbit/s Transceiver with Half-rate Support EXAMPLE ARCHITECTURE The figure below shows a multi-service switching platform using QuadPHY-II devices for backplane interconnect and client signal physical interfaces. As a serial backplane transceiver, the redundant high-speed links simplify the interface to a working and protect fabric. The 10GE line cards use the QuadPHYII as a PHY supporting XAUI on the line side and mating to a 10GE MAC using XGMII. Infiniband and Fibre Channel line cards applications are also shown. The halfrate mode of the QuadPHY-II enables 1 and 2 Gbit/s support using the same device. The other applications shown are a XAUI retimer and an XGMII extender where the MAC and Optics module separated by longer distance. APPLICATION EXAMPLE - MULTI-SERVICE SWITCHING PLATFORM 1Gig Fibre Channel Link * * * Switch Fabric Module 1G Fibre Channel Card ASIC / FPGA Optical Tranceiver Quad/ Octal PHYs Serial 10 Gigabit Ethernet LAN Line Card QuadPHY-II QuadPHY-II 10 GE 10Gig Serial LAN QuadPHY II QuadPHY-II QuadPHY-II Custom ASIC Upper Layer Functions 1Gig Fibre Channel Link FiberChannel MAC + Upper Layer Functions TBI MAC Optical Tranceiver XGMII XAUI 2 Gig Fibre Channel Link Switch Fabric Device 1G / 2G Fibre Channel Card QuadPHY-II QuadPHY-II QuadPHY-II ASIC / FPGA FiberChannel MAC + Upper Layer Functions TBI WDM 10 Gigabit Ethernet LAN Line Card QuadPHY-II 10 GE 4x3.125 WDM * * * Optical Tranceiver Custom ASIC Upper Layer Functions QuadPHY-II QuadPHY-II Optical Tranceiver 2 Gig Fibre Channel Link MAC * * * Gigabit Ethernet Card QuadPHY-II QuadPHY-II XGMII XAUI Gigabit Ethernet * * * 10 Gigabit Ethernet LAN Line Card QuadPHY-II XAUI Retimer QuadPHY-II QuadPHY-II Optical Tranceiver 10 GE LAN QuadPHY-II QuadPHY-II Optical Xceivers Quad/ Octal PHYs nxGE MACs Upper Layer Functions ASIC or FPGA Gigabit Ethernet GMII/TBI XGMII XAUI Redundant Switch Fabric Device XAUI EXTENDER * * * Infiniband Line Card QuadPHY-II QuadPHY-II QuadPHY-II Infiniband ASIC Upper Layer Functions 4x2.5Gig Fibre QuadPHY-II Optical Tranceiver MAC XGMII 4 x 2.5Gig Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PMC-2000791 (A4) (c) Copyright PMC-Sierra, Inc. 2001. All rights reserved. S/UNI is a registered trademark of PMC-Sierra Inc. SPECTRA, CHESS and QuadPHY-II are trademarks of PMC-Sierra, Inc. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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